vextoly/cryn
[# equal-width mixed signedness must be converted first #]
define main
make int64 a
make uint64 b
set -1
move a
write
set 1
move b
write
move a
read
push
move b
read
compare
stop
end
[# equal-width mixed signedness must be converted first #]
define main
make int64 a
make uint64 b
set -1
move a
write
set 1
move b
write
move a
read
push
move b
read
compare
stop
end